1. Filed of the Invention
The present invention relates to a storage device and a semiconductor device, and particularly to a storage device and a semiconductor device formed with a memory cell using a storage element that stores and retains information by a state of an electric resistance.
2. Description of the Related Art
In information devices such as computers and the like, a DRAM (Dynamic Random Access Memory) operating at a high speed and having a high density is widely used as a random access memory.
However, since DRAMs are volatile memories whose information disappears when power is turned off. Therefore nonvolatile memories whose information does not disappear are desired.
An FeRAM (ferroelectric memory), an MRAM (magnetic memory), a phase change memory, and a resistance change type memory such as a PMC (Programmable Metallization Cell), an RRAM or the like have been proposed as nonvolatile memories considered to be promising in the future.
These memories can retain information written therein for a long period of time even when no power is supplied. In addition, these memories, which are nonvolatile memories, eliminate a need for a refreshing operation, so that power consumption can be correspondingly reduced.
Further, a resistance change type nonvolatile memory such as a PMC, an RRAM or the like uses a material having a characteristic of changing a resistance value by being supplied with a voltage or a current as a storage layer for storing and retaining information, and has a relatively simple constitution in which two electrodes are provided with the storage layer interposed between the two electrodes, and a voltage or a current is applied to the two electrodes. It is therefore easy to miniaturize a storage element.
A PMC has a structure in which an ionic conductor containing a certain metal is interposed between two electrodes. Further, the metal contained in the ionic conductor is contained in one of the two electrodes, thereby using a characteristic in which an electrical property such as a resistance of the ionic conductor, a capacitance or the like changes when a voltage is applied between the two electrodes.
Specifically, the ionic conductor is composed of a solid solution of a chalcogen and a metal (for example amorphous GeS or amorphous GeSe), and one of the two electrodes contains Ag, Cu, or Zn (see JP-A-2002-536840, hereinafter referred to as Patent Document 1, for example).
As a RRAM structure, a structure has been introduced in which a polycrystalline PrCaMnO3 thin film, for example, is interposed between two electrodes, and the resistance value of the PrCaMnO3 recording film is greatly changed by applying a voltage pulse or a current pulse to the two electrodes (see “Novel Colossal Magnetoresistive Thin Film Nonvolatile Resistance Random Access Memory (RRAM)” written by W. W. Zhuang et al. in Technical Digest “International Electron Devices Meeting”, 2002, p. 193, hereinafter referred to as Non-Patent Document 1). Voltage pulses having different polarities are applied at the time of recording (writing) information and at the time of erasing information.
As another RRAM structure, a structure has been introduced in which SrZrO3 (single crystal or polycrystal) doped with a very small amount of Cr, for example, is interposed between two electrodes, and the resistance of the recording film is changed by passing current from these electrodes (see “Reproducible switching effect in thin oxide films for memory applications” written by A. Beck et al. in Applied Physics Letters, 2000, vol. 77, p. 139 to 141, hereinafter referred to as Non-Patent Document 2, for example).
Non-Patent Document 2 shows I-V characteristics of a storage layer, and shows that threshold voltages at times of recording and erasure are ±0.5 V. Even with this structure, information can be recorded and erased by applying a voltage pulse. A necessary pulse voltage is ±1.1 V, and a voltage pulse width is 2 ms. Further, high speed recording and erasing can be performed, and an operation with a voltage pulse width of 100 ns is reported. In this case, a necessary pulse voltage is ±5 V.
However, in the case of FeRAM, currently it is difficult to perform a nondestructive readout, and since a destructive readout is performed, a reading speed is slow. Moreover, the number of times of polarization inversion by reading or recording is limited, and thus there is a limitation to the number of times that FeRAM can be rewritten.
In the case of MRAM, recording needs a magnetic field, and the magnetic field is generated by a current passed through wiring. Therefore a large amount of current may be required when recording is performed.
A phase change memory performs recording by applying voltage pulses having a same polarity and different magnitudes. However, the phase change memory causes switching according to a temperature, and is therefore sensitive to a change in ambient temperature.
In the case of the PMC described in Patent Document 1, the crystallization temperature of amorphous GeS or amorphous GeSe is approximately 200° C., and the characteristics of the PMC are degraded when the ionic conductor is crystallized. Thus, the PMC may not endure a high temperature in a process of actually producing a memory element, for example a process of forming a CVD insulating film, a protective film or the like.
Each material for a storage layer proposed in the structure of the RRAMs described in Non-Patent Document 1 and Non-Patent Document 2 is a crystalline material. Therefore problems occur in that, for example, a heat treatment at approximately 600° C. has to be performed, it is very difficult to manufacture a single crystal of the proposed materials, and miniaturization is difficult due to effects of a grain boundary when a polycrystal is used.
Further, performing the recording or erasure of information by applying a pulse voltage in the above-mentioned RRAM is proposed. However, with the proposed structure, the resistance value of the storage layer after recording changes depending on the pulse width of the applied pulse voltage. Moreover, the fact that the resistance value after recording is thus dependent on the recording pulse width indirectly indicates that the resistance value will also change when the same pulse is repeatedly applied.
For example, in the above-mentioned Non-Patent Document 1, it is reported that when pulses having the same polarity are applied, the resistance value after recording changes greatly depending on pulse width. When the pulse width is small, that is, 50 ns or less, a rate of resistance change by recording is low. When the pulse width is large, that is, 100 ns or more, instead of being saturated to a constant value, the resistance value approaches a resistance value before recording as the pulse width is increased. Non-Patent Document 1 introduces characteristics of a memory structure in which a storage layer and a MOS transistor for access control are connected in series with each other and are disposed in the form of an array. In Non-Patent Document 1, it is reported that the resistance value of the storage layer after recording changes depending on the pulse width when the pulse width is changed in a range of 10 ns to 100 ns. When the pulse width is further increased, it is presumed from the characteristics of the storage layer that the resistance decreases again.
That is, the resistance value after recording in the RRAM is dependent on the magnitude and the pulse width of the pulse voltage, and therefore the resistance value after recording is varied when there are variations in the magnitude and the pulse width of the pulse voltage.
Accordingly, when the pulse voltage is shorter than about 100 ns, the rate of resistance change by recording is low, and thus variations in the resistance value after recording tend to produce effects. It is therefore difficult to perform the recording stably.
Accordingly, when recording is to be performed with such a short pulse voltage, a process of confirming (verifying) contents of information needs to be performed after the recording in order to perform the recording surely.
For example, a process of reading and confirming the contents of information (the resistance value of a storage layer) already recorded in a storage element is performed before recording, and the recording is performed in such a manner as to correspond to relation between the confirmed contents (resistance value) and contents to be recorded from now on (resistance value). Alternatively, for example, a process of reading and confirming the contents of information recorded in a storage element is performed after recording, and when the contents of information are different from a desired resistance value, re-recording is performed to correct the contents of information to the desired resistance value.
Thus, a long time is taken for recording, and it is difficult to perform overwriting of data or the like at a high speed, for example.
In order to solve the above-described problems, a storage device is proposed, the storage device including a memory cell formed by a storage element having a characteristic of changing a resistance value by applying a voltage equal to or higher than a threshold voltage between both ends of the storage element and a MOS transistor connected in series with the storage element, wherein when a voltage applied between both ends of the storage element and the MOS transistor is higher than a certain voltage which is higher than the threshold voltage, a combined resistance value of the storage element and the MOS transistor in the memory cell after the resistance value of the storage element is changed from a high state to a low state is a substantially constant value irrespective of magnitude of the voltage (see Japanese Patent Application No. 2004-22121, hereinafter referred to as Patent Document 2, for example). Such a storage device achieves stable recording, and shortens a time taken for recording information.